il08 CXD8879Q (1/4) gnd gnd dd v (+5v) dd v (+5v) gnd gnd gnd dd v (+5v) gnd dd v (+5v) gnd gnd 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 - top view - c-mos memory controller for frame synchronizer ********** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
pin no. i/o signal signal i/o no. pin signal i/o no. pin signal i/o no. pin CXD8879Q (2/4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 o o ? ? o o o o i i o o o o ? o o o o i i i i i/o i/o i/o i/o ? ? i/o i/o i/o i/o i i i i i i ? i i i i i i i i i i i i ? ? i i i i i o o o o o ? o o o o o i i o o o o o ? ? o o o o i i i i i ? i i i i i i i i o o o oy2 oy3 gnd oy4 oy5 oy6 oy7 ydl2 ydl3 oc0/ov0 gnd oc4/ov4 oc5/ov5 oc6/ov6 oc7/ov7 iv0/ic0 iv1/ic1 iv2/ic2 iv3/ic3 iu0/ou0 iu1/ou1 oc1/ov1 oc2/ov2 oc3/ov3 iu2/ou2 iu3/ou3 gnd iu4/ou4 iu5/ou5 iu6/ou6 iu7/ou7 ps mod gnd ck ild we2 we1 a1 a0 d7 d6 d5 d4 iv7/ic7 iv6/ic6 iv5/ic5 iv4/ic4 d3 d2 gnd d1 d0 hd vd fld old2 aux2 inh2 ben2o ben2e gnd aen2o aen2e inc2 hclr2 vclr2 tst clr old1 aux1 inh1 ben1o ben1e gnd aen1o aen1e inc1 hclr1 vclr1 blk ks ik iy0 iy1 gnd iy2 iy3 iy4 iy5 iy6 iy7 ydl0 ydl1 oy0 oy1 v dd dd v dd v dd v (v =+5v) dd
56 55 52 51 50 49 48 47 46 45 44 43 72 57 58 59 71 41 88 89 91 92 93 94 95 96 97 98 9 10 87 86 21 22 23 34 35 36 37 42 39 38 85 84 83 82 81 80 77 76 75 74 73 70 69 68 67 66 64 63 62 61 60 99 100 1 2 5 6 7 8 24 25 26 27 30 31 32 33 11 12 13 14 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 we1 we2 clr hd vd fld tst vclr1 hclr1 inc1 aen1e aen1o ben1e ben1o inh1 aux1 old1 vclr2 hclr2 inc2 aen2e aen2o ben2e ben2o inh2 aux2 old2 iy0 iy1 iy2 iy3 iy4 iy5 iy6 iy7 ydl0 ydl1 ydl2 ydl3 ik ks oy0 oy1 oy2 oy3 oy4 oy5 oy6 oy7 20 iv0/ic0 iv1/ic1 iv2/ic2 iv3/ic3 iv4/ic4 iv5/ic5 iv6/ic6 iv7/ic7 iu0/ou0 iu1/ou1 iu2/ou2 iu3/ou3 iu4/ou4 iu5/ou5 iu6/ou6 iu7/ou7 ild mod ps blk oc7/ov7 oc6/ov6 oc5/ov5 oc4/ov4 oc3/ov3 oc2/ov2 oc1/ov1 oc0/ov0 input a0, a1 blk ck clr d0-d7 fld hd ik ild iy0-iy7 ks mod ps tst vd we1, we2 ydl0-ydl3 ; address bus ; blanking ; clock ; clear ; data bus ; field (l ; even, h ; odd) ; holizontal synchronized ; 1 bit key ; load ; y data bus ; key select ; mode select (l ; 4:1:1 mode, h : 4:2:2 mode) ; parallel-serial / serial-parallel select (l ; s p, h ; p s) ; test ; vertical synchronized ; write enable ; y data delay output aen1e, aen2e aen1o, aen2o aux1, aux2 hclr1, hclr2 inc1, inc2 inh1, inh2 oc0/ov0-oc7/ov7 old1, old2 oy0-oy7 vclr1, vclr2 ; a ch even field enable ; a ch odd field enable ; mode 0,1 ; holizontal clear ; line increment ; inhibit ; serial data output of uv data at parallel-serial mode, ; mode 0 ; y data bus ; vertical clear input/output iu0/ou0-iu7/ou7 ; serial data output of u data at parallel-serial mode, CXD8879Q (3/4) ben1e, ben2e ben1o, ben2o ; b ch odd field enable ; b ch even field enable ; msb (aux bit) output of md 1? register. mode 2 mode 3 ; high bit output of load counter. ; h level output of line number set at vc1? h level output at all times when vc1?=0. parallel data output of v data at serial-parallel mode. ; l level when load counter output is 0 at load mode 1,2 ; low bit output of load counter at load signal mode 3 ; h level output of clock number set at ld1? h level output at all times when ld1?=0. h level output when aux1? (mode 3) is h level. iv0/ic0-iv7/ic7 ; parallel data input of v data at parallel-serial mode, serial data input of uv data at serial-parallel mode. parallel data output of u data at serial-parallel mode. register every v reset. signal for 4:1:1 mode of uv data converter. for 4:2:2 mode of uv data converter. register every h reset.
84 83 82 81 80 77 76 75 74 73 vclr1 hclr1 inc1 aen1e aen1o ben1e ben1o inh1 aux1 old1 old2 aux2 inh2 ben2o ben2e aen2o aen2e inc2 hclr2 vclr2 70 69 68 67 66 64 63 62 61 60 memory controller 1 memory controller 2 cpu i/f 2 2 8 46,45 44,43 52-47 72 56,55, a0, a1 we1, we2 d0-d7 clr 41 57 58 59 ck hd vd fld tst 71 y data delay 8 5-8 1,2, 99,100, oy0-oy7 iy0-iy7 91-96 88,89, 8 4 97,98, 9,10 ydl0-ydl3 87 ik 86 ks mod 39 ild 42 iu0-iu7 30-33 24-27, 8 8 20-23, 34-37 iv0-iv7 uv data converter oc0-oc7 11-14, 16-19 8 38 ps 85 blk /ov0-ov7 /ic0-ic7 /ou0-ou7 CXD8879Q (4/4)
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